Recently, in devices such as a high-speed wireless communication device and video device, an analog digital converter (hereinafter referred to as “ADC”) having a sampling frequency of the order of a gigahertz tends to be implemented by silicon-on-chip. Accordingly, the ADC that has high-resolution, low-power-consumption, and small-area ADC is demanded.
An SAR-ADC is well known as such ADC. The SAR-ADC is implemented by a comparator, a capacitive digital analog converter (hereinafter referred to as “DAC”), and a simple logic. The SAR-ADC attracts attention as the ADC that has low-power-consumption and small-area.
In the SAR-ADC, when a capacitive DAC has an ideal binary weight, an ideal digital output code is obtained with respect to an analog input signal. However, a signal (hereinafter referred to as “missing code”) to which AD (Analog to Digital) conversion is not performed may be generated because the weight actually changes according to a parasitic capacitance. Accordingly, in the SAR-ADC, a digital correction circuit that corrects the missing code is needed.
In the conventional digital correction circuit, the missing code is corrected by adding redundancy to the ADC using a redundant conversion algorithm. However, the conventional digital correction circuit that uses the redundant conversion algorithm becomes complicated, and therefore a circuit area of the SAR-DAC is enlarged.